I'm co-founder and CTO of YosysHQ GmbH, a company focusing on open source tools for digital design and formal verification.
Yosys Open SYnthesis Suite
Yosys is a framework for Verilog RTL synthesis. It has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains, including ASIC and FPGA synthesis and various formal verification tasks.
Project IceStorm aims at reverse engineering and documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files. The IceStorm flow (Yosys, Arachne-pnr, and IceStorm) is a fully open source Verilog-to-Bitstream flow for iCE40 FPGAs.
OpenSCAD is a software for creating solid 3D and 2D CAD objects. It is a "CAD Modeller for Programmers" as is is using a programming language to describe the CAD objects. By writing OpenSCAD code the designer can create parametric objects using a CSG design methodology.