Claire Xenia Wolf
Working on challenging projects that allow me to expand my skill set, at fair compensation and with enough free time to pursue my open source projects and academic/scientific work.
I have extensive experience with the following languages and technologies:
Verilog HDL, C/C++, Python, CUDA, FPGAs
Linux/UNIX Command Line, Shell Scripting, Git
SAT/SMT solving, Formal Verification
I'm also interested in, and have some experience with mathematical modelling, DSP algorithms, and machine learning. I'm excited whenever I find an excuse to spend time mastering a new mathematical method.
2021- Co-Founder & CTO at YosysHQ
YosysHQ provides Open Source EDA solutions for formal verification, synthesis and FPGA place-and-route.
2017-2020 Co-Founder & CTO at Symbiotic EDA
Symbiotic EDA provides Open Source EDA solutions for formal verification, synthesis and FPGA place-and-route.
2007-2017 Scientific Computing Engineer at RIEGL Laser Measurement Systems
Riegl is a leading manufacturer or LIDAR range finders and 3D scanners.
At Riegl I've been working on mathematical models, FPGA cores and GPGPU kernels, and did troubleshoot embedded Linux systems.
2003-2006 Sen. Software Engineer at LINBIT
LINBIT is an industry leader in high availability (HA) Linux solutions.
I've been working on improving the Linux HA software stack as part of my work at LINBIT.
Most notably, during my time at LINBIT I wrote the cluster file synchronization tool Csync2.
2001-2003 Lead developer / CTO at vocat.cc/dieStartseite.at
vocat.cc was a web startup creating a microblogging/linksharing/intranet platform based on microservices (years before the term "microservices" was coined).
1999-2003 UNIX/Linux Trainer and Consultant
Trainer at (among others) UNISYS, ETC, Global Knowledge (Austria and Switzerland), NTx
Freelance consultant and troubleshooter for all things Linux.
1996-1998 Sysop at magnet, an Austrian ISP
At magnet I was in charge of building and maintaining the entire UNIX/Linux server infrastructure and the back-end databases.
I taught a 2-year electronics course at metalab.at in 2010/2011 and 2012/2013.
2011-2016 I was teaching electronics at University of Applied Arts Vienna, Department of Digital Arts.
I have authored or co-authored scientific papers in more than one field and wrote an introductory electrical engineering textbook. See https://www.clairexen.net/publications for a list of notable publications.
Open Source Projects
Over the last two decades I have contributed to many Free and Open Source (FOSS) projects, including the Linux Kernel and other parts of the GNU/Linux system. I have also authored a few FOSS projects, such as:
A framework for Verilog synthesis and formal verification. Yosys is used as synthesis front-end in many FOSS HDL implementation flows, such as Qflow (ASICs) and the IceStorm flow (iCE40 FPGAs).
A complete FOSS end-to-end verilog synthesis flow for iCE40 FPGAs and a (reverse engineered) documentation for the iCE40 bit-stream format.
OpenSCAD is a software for creating solid 3D CAD models. OpenSCAD is not an interactive modeller. Instead it is something like a 3D-compiler that reads in a script file that describes the object and renders the 3D model from this script file. In 2010 I passed maintainership of OpenSCAD to Marius Kintel.
Other FOSS projects that I have authored include PicoRV32, SimpleVOut, Lib(X)SVF, EmbedVM, STFL, SPL, Csync2, and Trapdoor2.
Hobbies and other Interests
I've been the public relations officer for the Vienna branch of Chaos Computer Club (CCC) in 2003-2005.
Moderator and producer of "Nerds on Air" (a radio show on Radio Orange, a community radio station in Vienna) in 2004-2007.
Program chair for Linuxwochen Wien, a local FOSS/Linux conference, in 2004-2007.
I'm a founding member of metalab.at, a hackerspace in Vienna.
Member of Linux User Group Austria (luga.at), Mensa Austria (mensa.at), and Attac Austria (attac.at).
I'm a ham radio operator. My callsign is OE1CXW.
I play Go/Weiqi/Baduk online and Golf offline.