Publications

  • The design of scalar AES Instruction Set Extensions for RISC-V
    Ben Marshall and G. Richard Newell and Dan Page and Markku-Juhani O. Saarinen and Claire Wolf
    https://eprint.iacr.org/2020/930


  • Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs
    David Shah, Eddie Hung, C. Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic. FCCM 2019: 1-4.


  • Btor2 , BtorMC and Boolector 3.0
    Niemetz A., Preiner M., Wolf C., and Biere A. (2018)
    In: Chockler H., Weissenbacher G. (eds) Computer Aided Verification. CAV 2018.
    Lecture Notes in Computer Science, vol 10981. Springer, Cham

  • Toggle MUX: How X-Optimism Can Lead to Malicious Hardware.
    Christian Krieg, C. Wolf, Axel Jantsch, and Tanja Zseby
    Proceedings of the 54th Annual Design Automation Conference 2017 (DAC '17);
    download paper (pdf), doi:10.1145/3061639.3062328.

  • Malicious LUT: A Stealthy FPGA Trojan Injected and Triggered by the Design Flow
    Christian Krieg, C. Wolf, Axel Jantsch. Best paper award at ICCAD 2016.
    Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD 2016);
    download paper(pdf), doi:10.1145/2966986.2967054.

  • Online waveform processing for demanding target situations
    Martin Pfennigbauer, C. Wolf, Josef Weinkopf, Andreas Ullrich
    Proc. SPIE 9080, Laser Radar Technology and Applications XIX; and
    Atmospheric Propagation XI, 90800J (June 9, 2014);     doi:10.1117/12.2052994.

  • Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures.
    Johann Glaser and C. Wolf. In Jan Haase, editor, Models, Methods, and Tools for Complex Chip Design.
    Lecture Notes in Electrical Engineering. Volume 265, 2014, pp 201-221. Springer, 2013.

  • Enhancing online waveform processing by adding new point attributes
    Martin Pfennigbauer, C. Wolf, Andreas Ullrich
    Proc. SPIE 8731, Laser Radar Technology and Applications XVIII, 873104 (May 20, 2013)
    doi:10.1117/12.2015733.


  • Yosys - A Free Verilog Synthesis Suite
    C. Wolf, Johann Glaser. In Proceedings of Austrochip 2013. [download pdf]


  • Example-Driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic
    C. Wolf, Johann Glaser, Florian Schupfer, Jan Haase, Christoph Grimm
    2012 Forum on Specification and Design Languages (FDL)
    download paper (pdf), download presentation (pdf) (as presented at FDL 2012)

  • Linux Magazin Technical Review 04: High availability - Csync2,C. Wolf
    A german article about Csync2, a cluster synchronisation tool I wrote. (ISBN 978-3-939551-06-5, page 56-63)